1. Field of the Invention
The present invention relates to an adaptive digital filter circuit for performing a coefficient adaptation operation by adaptively updating the filter coefficient.
2. Description of the Related Art
A digital filter is a filter for performing a predetermined operation on input signals (input data) which are discrete from each other along the time axis and along the amplitude axis so as to output signals (filtered data) which are also discrete along the time axls and along the amplitude axis.
Among various digital filters, those in which the parameter for the predetermined operation is not fixed but varies over time such that intended output signals are obtained are called xe2x80x9cadaptive digital filtersxe2x80x9d, and such an intended output signal is called a xe2x80x9creference signalxe2x80x9d.
For example, an adaptive digital filter may be used for waveform equalization performed in a read/write channel LSI which is used in HDD (hard disk drive). In recent years, there is a demand for increasing the data transmission rate of digital devices such as HDD. Accordingly, there is a demand for increasing the operation speed of an adaptive digital filter circuit for performing the adaptive digital filtering process. Moreover, as portable personal computers become widespread. there is also a demand for reducing the size and power consumption of an adaptive digital filter circuit.
An adaptive digital filter circuit can be functionally divided into a filtering circuit and an adaptation circuit. The filtering circuit is a circuit for performing an operation using predetermined input data xi and coefficient data ai so as to obtain filtered data yxe2x80x2 and filter output data y. The adaptation circuit is a circuit for performing a coefficlent adaptation operation, i.e., adaptively updating the coefficient data ci so that the output of the filtering circuit, i.e., the filtered data yxe2x80x2, converges to an intended reference value Y.
The configuration and the operation of a conventional adaptive digital filter circuit will now be described with reference to the accompanying drawings.
FIG. 12 illustrates the configuration of the conventional adaptive digital filter circuit.
The adaptive digital filter circuit includes a pipelined filtering circuit 100 and a pipelined adaptation circuit 500. The pipelined filtering circuit 100 corresponds to the filtering circuit as described above. Specifically, the pipelined filtering circuit 100 performs an operation using the predetermined input data xi and coefficient data ci (i is an integer satisfying 1xe2x89xa6ixe2x89xa6n) so as to obtain the filtered data yxe2x80x2, The pipelined adaptation circuit 500 corresponds to the adaptation circuit as described above. Specifically, the pipelined adaptation circuit 500 adaptively updates the coefficlent data ci so that the output of the filtering circuit, i.e., the filtered data yxe2x80x2, converges to the intended reference value Y.
For each of the pipelined filtering circuit 100 and the pipelined adaptation circuit 500 of the conventional adaptive digital filter circuit, the entire operation process is performed in a pipelined process. This is because a pipelined process is most suitable for realizing the recent demand in the art, i.e., the increase in the operation speed of an adaptive digital filter circuit.
The term xe2x80x9cpipelined processxe2x80x9d as used herein refers to a process of successively receiving and processing a plurality of input signals to successively output the operation results, in which an input signal is received before outputting the operation result of a preceding input signal. Each input signal is processed through a plurality of stages provided in the circuit which are independent from one another, in which each stage processes the input signal and then passes the processed signal to the next stage.
The pipelined filtering circuit 100 receives the input data xi (i is an integer satisfying 1xe2x89xa6ixe2x89xa6n), the coefficient data ci (i is an integer satisfying 1xe2x89xa6ixe2x89xa6n) and a primary clock signal clk having a cyole of T. The pipelined filtering circuit 100 performs a predetermined operation using the received input data xi and the coefficient data cti so as to output the filtered data yxe2x80x2. The filtered data yxe2x80x2 is input to the pipelined adaptation circuit 500. The pipelined filtering circuit 100 performs a pipelined process based on the primary clock signal clk. FIG. 12 shows the filtered data yxe2x80x2 and the filter output data y as the outputs of the pipelined filtering circuit 100. The relationship between the filtered data yxe2x80x2 and the filter output data y is as follows. The filtered data yxe2x80x2 is the result of the predetermined operation as described above, and the filter output data y is a signal obtained by latching the filtered data yxe2x80x2 in response to the primary clock signal clk so as to adjust its timing before it is output to a subsequent circuit, e.g., a Viterbi decoding signal circuit in a read/write channel (R/W ch) LSI. The filtered data yxe2x80x2 before the latching process is used as the input to the pipelined adaptation circuit 500 so that it is possible to omit latching processes using registers and to avoid an unnecessary delay, thereby reducing the number of stages of the entire adaptive digital filter circuit and increasing the speed of the coefficient data update process.
The pipelined adaptation circuit 500 receives the input data xi (i is an integer satisfying 1xe2x89xa6ixe2x89xa6n), the output from the pipelined filtering circuit 100, i.e., the filtered data yxe2x80x2, the primary clock signal clk, and the secondary clock signal clkc. The pipelined adaptation circuit 500 adaptively updates the coefficient data ci so that the output of the pipelined filtering circuit 100, i.e., the filtered data yxe2x80x2, converges to the intended reference value Y. The pipelined adaptation circuit 500 performs a pipelined process based on the primary clock signal clk. In other words, in the pipelined filtering circuit 100 and in the pipelined adaptation circuit 500, data is passed from one stage to another in synchronization with the cycle of the primary clock signal clk. The pipelined adaptation circuit 500 uses the secondary clock signal clkc for latching the updated coeff icient data ci to be output later in a register. As will be more fully discussed below, the secondary clock signal clkc used for latching the coefficient data ci in a register is frequency-divided by the latency of the coefficient adaptation operation.
The operation of the adaptive digital filter circuit will now be described by describing each of the operation performed by the pipelined filtering circuit 100 and the operation performed by the pipelined adaptation circuit 500.
A commonly-employed adaptive digital filter circuit performs an operation based on an algorithm called xe2x80x9cLMS (least mean square)xe2x80x9d.
For any natural number 1, the input data xi (i is an integer satisfying 1xe2x89xa6ixe2x89xa6n) has a relationship represented by Expression 1 below.
x1[0]=x2[T]= . . . =xn[(nxe2x88x921)T]xe2x80x83xe2x80x83Expression 1
Herein, x2[T], for example, denotes input data x2 which is input at time t=T. T denotes the cycle of the primary clock signal clk.
The pipelined filtering circuit 100 receives the coefficient data ci (i is an integer satisfying 1xe2x89xa6ixe2x89xa6n) which is output from the pipelined adaptation circuit 500. The initial value of the coefficient data ci at the beginning of an operation may be a coefficient value which has been previously stored in the pipelined filtering circuit 100 or a coefficient value which has been previously stored in the pipelined adaptation circuit 500 and output to the pipelined filtering circuit 100.
The pipelined filtering circuit 100 caloulates the filtered data yxe2x80x2 according to Expression 2 below by using the input data xi and the coefficient data ci.
xe2x80x83yxe2x80x2=xcexa3cixc2x7xixe2x80x83xe2x80x83Expression 2
Upon receiving the filtered data yxe2x80x2 which is obtained by the operation represented by Expression 2 above, the pipelined adaptation circuit 500 adaptively updates the coefficient data ci so that the value thereof converges to the intended reference value Y. The update of the coefficient data is performed by using the amount of coefficient change xcex94ci (i is an integer satisfying 1xe2x89xa6ixe2x89xa6n), which is obtained by an operation represented by Expression 3 below. The coefficient adaptation operation according to Expression 3 below is the algorithm called xe2x80x9cLMS (least mean square)xe2x80x9d.
xcex94ci=xcexcxc2x7xcex5xc2x7xixe2x80x83xe2x80x83Expression 3
Herein, the amount of coefficient change xcex94ci denotes the amount of change in the coefficient data ci, and xcexc denotes a convergence coefficient, which is a positive constant. The error xcex5 denotes an errorbetween the intended reference value Y and the filtered data yxe2x80x2 and can be represented by Expression 4 below.
xcex5=Yxe2x88x92yxe2x80x2xe2x80x83xe2x80x83Expression 4
The updated coefficient data cixe2x80x2 can be obtained according to Expression 5 below by using the coefficient data ci and the amount of coefficient change xcex94ci which is obtained by the operation represented by Expression 3.
cixe2x80x2=ci+xcex94cixe2x80x83xe2x80x83Expression 5
It is known in the art that the following relationship holds when the coefficient data ci is updated according to Expression 5.
xcex94(xcex52)/xcex94cixe2x89xa60xe2x80x83xe2x80x83Expression 6
Thus, xcex52 always decreases, and the filtered data yxe2x80x2 approaches the intended reference value Y.
FIG. 13 illustrates the configuration of the pipelined adaptation circuit 500. The pipelined adaptation circuit 500 performs operations respectively represented by Expressions 3-5 above.
The top of FIG. 13 shows a time axis which represents the amount of time required from the point in time when the pipelined adaptation circuit 500 receives the input data xi to the point in time when the data reaches the respective elements. The time axis is scaled based on the cycle T of the primary clock signal clk. For example, where the input data xi is input at time t=0, the coefficient updated by the pipelined adaptation circuit 500 is latched by a register 522 in the last stage at time t=11T.
The pipelined adaptation circuit 500 performs the operations respectively represented by Expressions 3-5 by using the input data xi (i is an integer satisfying 1xe2x89xa6ixe2x89xa6n), the output from the pLpelined filtering circuit 100, i.e., the filtered data yxe2x80x2, the intended reference value Y, and the coefficient data ci (i is an integer satisfying 1xe2x89xa6ixe2x89xa6n) which is held in the internal register 522. As described above, the pipelined adaptation circuit 500 adaptively updates the coefficient data ci so that the output of the pipelined filtering circuit 100, i.e., the filtered data yxe2x80x2, converges to the intended reference value Y.
The pipelined adaptation circuit 500 includes a plurality of registers (e.g., 510, 512, 516) for latching data having the predetermined number of bits, a plurality of multipliers (e.g., 518) for multiplication of two or more data, a plurality of adders (e.g., 514) for addition of two or more data, and a plurality of clipping circuits (e.g., 520) for an overflow process. The number of registers is proportional to the number of taps (i.e., the number of input data xi) and to the number of pipeline stages. In the pipelined adaptation circuit 500 shown in FIG. 13, the number of taps is seven and the number of pipeline stages is eleven.
The registers (e.g., 510, 512, 516) of the pipelined adaptation circuit 500 latch data upon receiving a pulse of the primary clock signal clk. Specifically, each of the registers holds data which was input at the instance of low-to-high transition of the primary clock signal clk, and outputs the held value until the next low-to-high transition of the primary clock signal clk. Since the primary clock signal clk has a cycle of T. data having a predetermined number of bits (e.g., 6 bits) is latched at time t=kT (k is an integer satisfying 1xe2x89xa6k). For example, the register 510 latches the input data xi at time t=T. in response to the pulse of the primary clock signal clk at time t=T. The register 512 latches the input data xi which has been latched by the register 510 at time t=T in response to the low-to-high transition of the pulse of the primary clock signal clk at time t=2T. In FIG. 13, each of the other elements indicated by the same symbol as the registers 510 and 512 is also a register having the same function.
The multiplier (e.g., 518) and the adder (e.g., 514) receive two or more data and perform multiplication and addition, respectively, of the received data, so as to output the results thereof.
The clipping circuit (e.g., 520) is used for an overflow process for the signal to be output before externally outputting the coefficient data ci which has been updated by the pipelined adaptation circuit 500.
Referring to FIG. 13, upon receiving the input data xi and the primary clock signal clk, the register 510 latches the value of the input data xi. The signal latched by the register 510 is then passed to and latched by the next register 512 in synchronization with the cycle of the primary clock signal clk. This operation is repeated until time t=6T. Since the pipelined adaptation circuit 500, which performs a pipelined process, successively receives new input data xi for every cycle T of the primary clock signal clk, two data latched in adjacent registers are data which have been input to the pipelined adaptation circuit 500 at xe2x80x98adjacentxe2x80x99 (i.e., slightly different) timings.
The pipelined adaptation circuit 500 needs to obtain the error xcex5 according to Expression 4 before performing the operation of Expression 3. The operation of Expression 4 is performed by using the adder 514 at time t which satisfies 5T less than t less than 6T. This is because there is a time shift (5T in this case) between the point in time when the input data xi is input and the point in time when the pipelined adaptation circuit 500 receives the filtered data yxe2x80x2 (i.e., the output of the pipelined filtering circuit 100), which 1a required for the operation of Expression 4. This time shift occurs due to the amount of time required for the pipelined filtering circuit 100 to generate the filtered data yxe2x80x2 from the input data xi, and is dependent on the number of stages of the pipelined filtering circuit 100. In this specification, this time shift is referred to as a xe2x80x9clatencyxe2x80x9d.
The error e obtained by the operation of Expression 4 is latched by the register 516 at time t=6T in response to the low-to-high transition of the primary clock signal clk at time t=6T. Using the latched error xcex5, the xcex5 xi part of the operation of Expression 3 is performed at time t which satisfies 6T less than t less than 7T. The input data xi input at time t=0 is latched by a group of registers until the error xcex5 is obtained by using the filtered data yxe2x80x2 which is calculated from the same input data xi.
Then, the operation xcexcxc2x7(xcex5xc2x7xi) of Expression 3 is performed at time t which satisfies 8T less than t less than 9T. and the amount of coefficient change xcex94ci is latched by a register at time t=9T. Finally, the operation of Expression 5 is performed at time t which satisfies 9T less than t less than 10T by using the previously obtained coefficient data ci and the amount of coefficient change xcex94ci, and the result of the operation is subjected to an overflow process by the clipping circuit 520. The updated coefficient data cixe2x80x2, i.e., the value after the overflow process, is latched by a register in response to the low-to-high transition of the clock signal clkc at time t=11T, and then output as the coefficient data ci. The above-described operations are performed based on the primary clock signal clk and the secondary clock signal clkc.
FIG. 14 is a timing diagram illustrating the timings of the signals processed in the pipelined adaptation circuit 500.
The primary clock signal clk is a pulse signal having a cycle of T.
After the amount of time 5T from the reception of the input data xi, the filtered data yxe2x80x2 is generated by the pipelined filtering circuit 100 and input to the pipelined adaptation circuit 500. Thus, 5T is the amount of time required for the pipelined filtering circuit 100 (FIG. 12) to generate the filtered data yxe2x80x2 since the reception of the input data xi.
According to the timing of the coefficient data ai shown at the bottom row of the timing diagram, it is shown that the amount of time required for given coefficient data ci to be processed into new updated coefficient data ci is 11T.
A pipelined process essentially requires registers for storing the intermediate results of the process. In addition, the coefficient adaptation operation as described above requires a group of registers, as those shown in FIG. 13, in the pipelined adaptation circuit for matching the timing of the input data xi with that of the filtered data yxe2x80x2. Since the number of registers is proportional to the number of pipeline stages, an increase in the number of pipeline stages makes it necessary to increase the number of registers accordingly. Moreover, it is necessary to provide a number of registers according to the number of bit of each data. As a result, the number of registers included in the pipelined adaptation circuit 500 of FIG. 13 is 651.
Since most of these registers are used simultaneously in a pipelined process, the registers consume a substantial amount of power. Thus, the employment of a pipelined process to increase the process speed inevitably increases the number of registers. As a result, it is difficult to reduce the power consumption when employing a pipelined process.
Moreover, an increase in the number of pipeline stages increases the amount of time required from the reception of an input signal to th update of the coefficient, and also increases the amount of time required for a coefficient to converge from its initial value to a value such that an intended output value can be obtained.
If the frequency of the operation clock is increased in response to the recent demand in the art, i.e., the increase in the operation speed of a circuit, the number of times each register in the circuit is operated increases, thereby increasing the power consumption of the circuit. Then, the amount of heat generated in the circuit also increases, thereby making it difficult to further increase the integration density of the circuit and reduce the size of the circuit.
According to one aspect of this invention, an adaptive digital filter includes: a pipelined filtering section for performing a filtering operation based on input data and coefficient data so as to output filtered data; and a non-pipelined adaptation section for outputting the coefficient data to the pipelined filtering section by performing a coefficient adaptation operation in a non-pipelined process based on the input data and the filtered data so that the filtered data output from the pipelined filtering section converges to a predetermined reference value.
In one embodiment of the invention, the adaptive digital filter further comprises a secondary clock signal generation circuit for receiving a primary clock signal having a predetermined frequency, generating at least one secondary clock signal synchronized with the primary clock signal and having a frequency which is different from the predetermined frequency, and outputting the at least one secondary clock signal to the non-pipelined adaptation section. The pipelined filtering section operates according to the primary clock. sgnal. The non-pipelined adaptation section operates according to the at least one secondary clock signal.
In one embodiment of the invention, the at least one secondary clock signal includes: a first secondary clock signal for latching the input data; a second secondary clock signal for latching the filtered data; and a third secondary clock signal for latching a result of the coefficient adaptation operation.
In one embodiment of the invention, the pipelined process has a predetermined number of stages. A relationship between a phase of the first secondary clock signal and a phase of the second secondary clock signal is dependent on the number of stages. A relationship between the phase of the second secondary clock signal and a phase of the third secondary clock signal is dependent on an amount of time required for the coefficient adaptation operation.
In one embodiment of the invention, at least a part of the coefficient adaptation operation is performed during a period of time from a point in time when the input data is latched in response to the first secondary clock signal to a point in time when the filtered data is latched in response to the second secondary clock signal.
In one embodiment of the invention, the non-pipelined adaptation section includes: an error calculation section for calculating and outputting an error between the filtered data and the predetermined reference value; a latency compensation section for outputting delayed data obtained by delaying the input data by at least an amount of time which is determined based on the number of stages; and an adaptation operation section for performing the coefficient adaptation operation based on the delayed data and the error so as to output the coefficient data.
In one embodiment of the invention, the adaptive digital filter further includes a secondary clock signal generation circuit for receiving a primary clock signal having a predetermined frequency, generating at least one secondary clock signal synchronized with the primary clock signal and having a frequency which is different from the predetermined frequency, and outputting the at least one secondary clock signal to the non-pipelined adaptation section. The error calculation section includes a register for latching the filtered data in response to the secondary clock signal.
In one embodiment of the invention, the adaptive digital filter further includes a secondary clock signal generation circuit for receiving a primary clock signal having a predetermined frequency, generating at least one secondary clock signal synchronized with the primary clock signal and having a frequency which is different from the predetermined frequency, and outputting the at least one secondary clock signal to the non-pipelined adaptation section. The latency compensation section includes a register for latching the input data in response to the secondary clock signal.
In one embodiment of the invention, the adaptive digital filter further includes a secondary clock signal generation circuit for receiving a primary clock signal having a predetermined frequency, generating at least one secondary clock signal synchronized with the primary clock signal and having a frequency which is different from the predetermined frequency, and outputting the at least one secondary clock signal to the non-pipelined adaptation section. The adaptation operation section includes a register for latching in response to the secondary clock signal a result of the coefficient adaptation operation performed based on the delayed data and the error.
In one embodiment of the invention, the coefficient adaptation operation is implemented by a software program.
In one embodiment of the invention, the calculation of the error between the filtered data and the predetermined reference value is implemented by a software program.
In one embodiment of the invention, a phase and a cycle of the first secondary clock signal, a phase and a cycle of the second secondary clock signal, and a phase and a cycle of the third secondary clock signal can be set by a software program.
In one embodiment of the invention, the coefficient adaptation operation is implemented by a software program, and the software program executes an operation of waiting for an input of a pulse of the first secondary clock signal.
In one embodiment of the invention, the coefficient adaptation operation is implemented by a sof tware program, and the software program executes an operation of waiting for an input of a pulse of the second secondary clock signal.
In one embodiment of the invention, the coefficient adaptation operation is performed based on an LMS algorithm.
In one embodiment of the invention, the coefficient adaptation operation is performed based on an RLS algorithm.
Thus, the invention described herein makes possible the advantage of providing an adaptive digital filter circuit whose power consumption is reduced by reducing the number of registers and the frequency with which they are operated, and in which the amount of time required for a coefficient to converge is reduced by reducing the number of pipeline stages.